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1 www.pericom.com 03/24/14 features yy support up to 3.4gbps tmds serial link compliant with hdmi 1.4b requirement yy hdmi 1-to-2 splitter or 1-to-2 demux with equalization & pre-emphasis up to 340 mhz clock yy ac or dc coupled diferential signaling input yy confgurable tmds output signal with port selection, pre-emphasis, voltage swing, slew rate control yy support squelch mode with built-in clock detector yy control status register controlled by pin strap or i 2 c mode programming yy esd protection on i/o pins to connector: 8kv contact per iec6100-4-2 and 2kv hbm yy supply voltage: 3.3v yy industrial temperature range: -40 o c to 85 o c yy packaging (pb-free & green): 56-contact tqfn (zb56) general description pericom semiconductors pi3hdx412bd, active-drive switch solution is targeted for high-resolution video net - works that are based on hdmi tm /dvi standards, and tmds signal processing. the pi3hdx412bd is an active single tmds channel to two tmds channel splitter and demux with hi-z outputs. the device drives differential signals to multiple video display units. it provides controllable output swing levels that can be con - trolled through pin control or i2c control, depending on the mode select pin. this solution also provides a unique advanced pre-emphasis technique to increase rise and fall times. the maximum hdmi tm /dvi data rate of 3.4gbps provides a 1920x1080 @60hz resolution or 4k @30hz required for 4k hdtv and pc graphics products. due to its active uni- directional feature, this switch is designed for usage only for the video drivers side. for pc graphics application, the device sits at the drivers side to switch between multiple dis - play units, such as pc lcd monitor, projector, tv, etc. pi3hdx412bd ensures transmitting high bandwidth video streams from pc graphics source to end display units. it will also provide enhanced robust esd/eos protection, which is required by many consumer video networks today. hdmi input hdmi outputs pi3hdx412b pi3hdx414 pi3hdx414 port_a port_b vdd d0p1 d0n1 gnd clkp1 clkn1 vdd d2p2 d2n2 gnd d1p2 d1n2 vdd d0p2 vdd sel_out rout_sel vdd18 eq2/scl_ctl eq1/sda_ctl gnd vdd gnd vdd clkn2 clkp2 gnd d0n2 oe sel1 dr gnd emp2/i2c_adr3 emp1/i2c_adr2 sw2/i2c_adr1 sw1/i2c_adr0 vdd d2p1 d2n1 gnd d1p1 d1n1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 ms vdd gnd d2p d2n vdd d1p d1n d0p d0n vdd clkp clkn gnd pi3hdx412bd tqfn- 56 application block diagram pi3hdx412bd package & pinout all trademarks are property of their respective owners. pi3hdx412bd hdmi 1.4b 1:2 splitter/demux for 3.4gbps data rate with equalization & pre-emphasis 14-0020
2 www.pericom.com 03/24/14 tmds in/out pin assignment pin # pin name type description 4 d2p i input port. tmds clock and data input pins. when input termination resistor (rt = 50 ohm) tied to vdd or gnd, rpd=200 kohm shall be "off" state. i2c registers can control rt and rpd on/off state. 5 d2n i 7 d1p i 8 d1n i 9 d0p i 10 d0n i 12 clkp i 13 clkn i 25 clkn2 o output port 1. tmds clock and data output pins. rout_sel pin en- ables output termination resistor (rout=50 ohm). 26 clkp2 o 28 d0n2 o 29 d0p2 o 31 d1n2 o 32 d1p2 o 34 d2n2 o 35 d2p2 o 37 clkn1 o output port 2. tmds clock and data output pins. rout_sel pin en- ables output termination resistor (rout=50 ohm). 38 clkp1 o 40 d0n1 o 41 d0p1 o 43 d1n1 o 44 d1p1 o 46 d2n1 o 47 d2p1 o note: in tmds data and clock diferential pair, the polarity +/- (or p/n) of each pair can use interchangeably. when input tmds input clock polarity +/- pin swaps, output tmds clock of port 1 and port 2 shall swapped accordingly. pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
3 www.pericom.com 03/24/14 pin # pin name type description 1 ms i mode selection pin. internal pull-up at 100k ohm. "high" : i 2 c control mode selection "low" : pin control mode selection 19 20 eq2/scl_ctl eq1/sda_ctl io shared pin. eq2 pin or i 2 c clock pin. i 2 c pin is compatible with standard i 2 c- bus specifcation, up to 400 kbps. pin#1 ms sets "high" : pin#19 assigns to scl_ctl pin pin#1 ms sets "low" : pin#19 assigns to eq2 pin internally pull-up at 100 kohm and pull-down at 100 kohm. pin control eq setting table is shown below. "m" is tri-state. eq2 (pin# 19) eq1 (pin# 20) equalization setting (db) pin#1 ms = "low" 0 m 2.5 0 0 5 m 0 7.5 0 1 10 m m 12.5 1 0 15 1 m 17.5 1 1 20 49 50 51 52 sw1/i2c_adr0 sw2/i2c_adr1 emp1/i2c_adr2 emp2/i2c_adr3 i shared pin. sw or emp or i2c_adr pins. when pin#1 ms="high" : these shared pins assign to i2c_adr[3:0] when pin#1 ms="low" : these shared pins assign to sw1/2 and emp1/2 tese sw2 and sw1 pins control output voltage swing adjustment as following table. tese sw pins have internal pull-up 100k ohm. sw2 (pin#50) sw1 (pin#49) output voltage swing 0 0 50 0 mv 0 1 -10 % 1 0 +10 % 1 1 +20 % control pins pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
4 www.pericom.com 03/24/14 pin # pin name type description 49 50 51 52 (continued) i emp2 and emp1 pins control output voltage pre-emphasis. tese pins have internally pull-up 100 kohm. emp2 (pin#52) emp1 (pin#51) pre-emphasis setting (db) 0 0 0 0 1 1.5 1 0 2.5 1 1 3.5 56 oe i output enable control pin. internally pull-up at 100 kohm. "high" : output port enable "low" : turn of rout and rt(termination resistor). tmds receiver and tmds output drivers are "off" state. 54 dr i direction control pin "high" : all ports are active at same time "low" : output ports are controlled by sel1 (pin#55) control 55 sel1 i port 1 or port 2 output enable selection pin. internal pull-up at 100 kohm. "high" : enable output port 2 "low" : enable output port 1 16 sel_out o sel_out pin. i 2 c register ofset 0x00 bit[5] can control this pin status. ofset 0x00 bit[5] ="1" : enable output port 1 output ofset 0x00 bit[5] ="0" : disable output port 1 output 17 rout_sel i source termination selection pin. internal pull-up at 100k ohm. "high" : source termination output (rout) resistor is "on", connect to vdd in output driver "low" : source termination output (rout) resistor is "off". open-drain output driver is open drain pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
5 www.pericom.com 03/24/14 power/ground pins pin # pin name type description 18 vdd18 power ldo output pin for internal core supplier. add external 4.7 uf ca- pacitor to gnd 3,14,21,23,27,33,39,45,53 gnd ground ground pins 2,6,11,15,24,30,36,42,48 vdd power 3.3v power supply pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
6 www.pericom.com 03/24/14 demux i2c controller control & status register ldo clkp/n d[0:2]p/n scl_ctl sda_ctl eq#,ms,dr, sel# sw.emp# control pins rt rpd rout rout vdd vdd vdd or gnd gnd vdd vdd18 block diagram pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
7 www.pericom.com 03/24/14 functional description squelch mode : output disable (squelch) mode uses tmds clock channel signal detection. when low voltage levels on the tmds input clock signals are detected, squelch state enables and tmds output port signals shall disable; when the tmds clock input signal levels are above a pre-determined threshold voltage, output ports shall return to the normal voltage swing levels. when enable squelch mode, input termination resistor will be enabled together. when squelch is disabled through i2c register programming rx_set[1]="1" and no tmds input signal condition, tmds d[0:2]p/n will be undetermined status. in squelch state, tmds output is high impedance state or tmds output port shall 50 ohm pull-up at source termination output. function control table oe ms dr sel1 hdmi outputs 0 x x x all port disable pin cotrol mode 1 0 1 x all ports enable 1 0 0 0 enable port 1 1 0 0 1 enable port 2 i2c control mode 1 1 x x i2c programming mode pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
8 www.pericom.com 03/24/14 i 2 c register control programming i 2 c register control pin name i/o description scl_ctl i i2c clock, compatible with i2c-bus specification, up to 400 kb/s sda_ctl io i2c data, compatible with i2c-bus specification, up to 400 kb/s i2c_adr[3:0] i i2c control address setting byte output : 0x00 - 0x07 o i2c control registers output i 2 c address byte b[7] msb b[6] b[5] b[4] b[3] b[2] b[1] b[0] (r/w) address byte 1 0 1 a3 a2 a1 a0 1/0* note: read "1", write "0" pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
9 www.pericom.com 03/24/14 ofset name description power up condition type 0x00 config[7:0] [7] enable tmds standby mode. in standby mode, tmds equalizer and output driver shall power down. "0": standby mode "1": normal mode [6] reserved [5] output tmds port 1 select "0": disable "1": enable [4] output tmds port 2 selected "0": disable "1": enable [3] reserved [2:0] reserved 0xff r/w 0x01 rx_set[7:0] tmds receiver equalization setting registers [7] disable input port input termination resistors "0" : enable rpd connection "1" : disable rpd connection [6] tmds input termination v-bias selection "0": connect to gnd "1": connect to vdd [5] v-bias register selection enable "0": bit[6] control disable "1": bit[6] control enable [4:2] eq programmable setting b[4:2] eq setting (db) 000 2.5 001 5 010 7.5 011 10 100 12.5 101 15 110 17.5 111 20 [1] squelch control bit "0": squelch enable "1": squelch disable [0] reserved 0x00 r/w 0x02 reserved [7:0] reserved 0x00 r/w pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
10 www.pericom.com 03/24/14 ofset name description power up condition type 0x03 tx_set[7:0] for port1 tmds port 1 output setting [7] tmds output control "0": open drain "1": double termination [6:4] tmds output pre-emphasis control "000": 0 db "001": 1.5 db "010": 2.5 db "011": 3.5 db "1xx": 6 db (750 mvpp swing) [3:2] tmds output swing setting "00": 500 mv as default "01": -10% "10": +10% "11": +20% [1:0] tmds output slew rate setting "00": as default "01" / "10": + 5% "11": +10% 0x00 r/w 0x04 tx_set[7:0] for port2 tmds port 2 output setting [7] tmds output control "0": open drain "1": double termination [6:4] tmds output pre-emphasis control "000" : 0 db "001" : 1.5 db "010" : 2.5 db "011" : 3.5 db "1xx" : 6 db ( 750 mvpp swing) [3:2] tmds output swing setting "00" : 500 mv as default setting "01" : -10% "10" : +10% "11" : +20% [1:0] tmds output slew rate setting "00" : default setting "01" / "10" : + 5% "11" : +10% 0x00 r/w 0x05 reserved [7:0] reserved 0x00 r/w 0x06 reserved [7:0] reserved 0x0f r/w 0x07 reserved [7:0] reserved 0x00 r/w pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
11 www.pericom.com 03/24/14 ack ack ack no ack r / w dev sel data out 1 data out n start stop 1. read sequence ack ack ack ack r / w dev sel data in 1 data in n start stop 2. write sequence i 2 c data transfer pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
12 www.pericom.com 03/24/14 electrical characteristics t j =25 c unless otherwise noted dc specifications vdd=3.3v +/- 10% symbol parameter test conditions min. typ. max. units v dd operation voltage 3.0 3.3 3.6 v i dd vdd supply current 250 290 ma i ddq vdd quiescent current oe = 1, no input signal 50 80 ma i stb standby mode oe = 0 1 5 ma tmds diferential pins v oh single-ended high level output voltage vdd = 3.3 v, rout=50 vdd-10 vdd+10 mv vol single-ended low level output voltage vdd-600 vddC400 mv vsw ing single-ended output swing voltage 400 600 mv vod(o) overshoot of output diferential voltage 180 mv vod(u) undershoot of output diferential volt- age 200 mv voc(ss) change in steady-state common- mode output voltage between logic states 5 mv ios short circuit output current -12 12 ma ios short circuit output current at double termination mode -24 24 ma absolute maximum ratings supply voltage to ground potential ........................... 4.5v d c sig voltage ............................... C0.5v t o v dd +0.5v storage temperature .............................. C65c t o +150c operating temperature .............................. -40 t o +85c note: stresses greater than those listed under maximum rat- ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. ex- posure to absolute maximum rating conditions for extended periods may afect reliability. thermal characteristics symbol parameter ratings units t jmax junction temperature 125 c r jc termal resistance, junction to case 5 c/w r ja termal resistance, junction to ambient 24 pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
13 www.pericom.com 03/24/14 symbol parameter test conditions min. typ. max. units vi(open) single-ended input voltage under high impedance input or open input il = 10 ua vdd-10 vdd+10 mv rt input termination resistance vin = 2.9 v 45 50 55 ohm ioz leakage current with hi-z i/o vdd = 3.6 v, oe = 0 30 100 fa control pins (oe, sel1, emp2, emp1, sw2, sw1, ms) i ih high level digital input current v ih =v dd -10 10 fa i il low level digital input current v il = gnd -50 10 fa v ih high level digital input voltage 2.4 v v il low level digital input voltage 0 0.8 v ac specifications symbol parameter test conditions min. typ. max. units tpd propagation delay 2000 ps t r diferential output signal rise time (20% - 80%), 0 db / open drain v dd =3. 3v, rout=50 ohm 117 ps t f diferential output signal fall time (20% - 80%), 0 db / open drain 117 ps t sk(p) pulse skew 15 50 ps t sk(d) intra-pair diferential skew 25 50 ps t sk(o) inter-pair diferential skew 100 ps t sx select to switch output 550 ns t en enable time 1 10 us t dis disable time 50 ns tjit_clk(pp) peak-to-peak output jitter clk residual jitter data: 3.4 gbps data pattern clock: 340 mhz 10 ps tjit_data(pp) peak-to-peak output jitter date residual jitter 28 ps note: 1. overshoot of output diferential voltage v od(o) = (v swing(max) *2) * 15% 2. undershoot of output diferential voltage v od(o) = (v swing(min) *2) * 25% pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
14 www.pericom.com 03/24/14 inter-pair skew definition intra-pair skew definition test setup of dc-coupled tmds input measurement pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
15 www.pericom.com 03/24/14 rise/fall time and single-ended swing voltage typical splitter application pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
16 www.pericom.com 03/24/14 power supply decoupling circuit it is recommended to put 0.1 f decoupling capacitors on each vdd pins of our part, there are four 0.1 f decoupling capacitors are put in figure 1 with an assumption of only four vdd pins on our part, if there is more or less vdd pins on our pericom parts, the number of 0.1 f decoupling capacitors should be adjusted according to the actual number of vdd pins. on top of 0.1 f decoupling capacitors on each vdd pins, it is recommended to put a 10 f decoupling capacitor near our parts vdd, it is for stabilizing the power supply for our part. ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. but, it is optional and de- pends on the power supply conditions of other circuits. requirements on the de-coupling capacitors tere is no special requirement on the material of the capacitors. ceramic capacitors are generally being used with typi- cally materials of x5r or x7r. recommended power supply decoupling capacitor diagram pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
17 www.pericom.com 03/24/14 layout and decoupling capacitor placement consideration yy each 0.1 f decoupling capacitor should be placed as close as possible to each vdd pin. yy vdd and gnd planes should be used to provide a low impedance path for power and ground. yy via holes should be placed to connect to vdd and gnd planes directly. yy trace should be as wide as possible yy trace should be as short as possible. yy te placement of decoupling capacitor and the way of routing trace should consider the power fowing criteria. yy 10 f capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 f capacitors. yy avoid the large current circuit placed close to our part; especially when it is shared the same vdd and gnd planes. since large current fowing on our vdd or gnd planes will generate a potential variation on the vdd or gnd of our part. decoupling capacitor placement diagram pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
18 www.pericom.com 03/24/14 ordering information ordering code package code package description pi3hdx412bdzbe zb 56-pin, pb-free & green tqfn, source termination type notes: termal characteristics can be found on the company web site at www.pericom.com/packaging/ pi3hdx412b : root part number -d/e : d= source termination tmds top mount type, e = source termination tmds bottom mount type -zb = 56-pin tqfn package type -e = pb-free and green adding an -x sufx = tape/reel type 1 description: 56-contact, thin fine pitch quad flat no-lead (tqfn) package code: zb (zb56) document control #: pd-2008 revision: e date: 03/18/09 package mechanical: 56-pin tqfn (zb56) note: for latest package info, please check: http://www.pericom.com/products/packaging pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
19 www.pericom.com 03/24/14 related products information part number product description pi3hdx414 hdmi 1.4b 3.4gbps splitter 1:4 with signal conditioning pi3hdx1204 hdmi 2.0 redriver for 6gbps application pi3hds20412 wide voltage range displayport & hdmi 2.0 video switch pi3hdx511a hdmi 1.4b 3.4gbps redriver and dp++ level shifer pi3eqxdp1201 displayport 1.2 re-driver with built-in aux listener pi3vdp1430 dual mode displayport to hdmi level shifer and re-driver pi3vdp3212 2-lane displayport1.2 compliant passive switch pi3vdp12412 4-lane displayport1.2 compliant passive switch pi3hdmi521 hdmi 1.4b 3.4gbps 2:1 switch/re-driver with built-in arc and fast switching support PI3HDMI336 active hdmi 3:1 switch/re-driver with i 2 c control and arc transmitter disclaimer information in this document is provided in connection with pericom product. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is grant- ed by this document. except as provided in pericoms terms and conditions of sale for such products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual prop- erty right. pericom may make changes to specifcations and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefned. pericom reserves these for future defnition and shall have no responsibility whatsoever for conficts or incompatibilities arising from future changes to them. te products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifcation. current characterized errata are available on request. contact your local pericom sales ofce or your distributor to obtain the latest specifcations and before placing your product order. copyright 2014 pericom corporation. all rights reserved. pericom and the pericom logo are trademarks of pericom corpo- ration in the u.s. and other countries. pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020
20 www.pericom.com 03/24/14 product status definitions datasheet identification product status definition advanced information formative / in design datasheet contains the design specifications for product de- velopment. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. pericom semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. pericom semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontin- ued by pericom semiconductor. the datasheet is for reference information only. pi3hdx412bd 3.4gbps hdmi 1.4b 1:2 splitter/demux with equalization & pre-emphasis all trademarks are property of their respective owners. 14-0020

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